Design and design methods for unified multiplier and inverter and its application for HECC

This paper describes two novel architectures for a unified multiplier and inverter (UMI) in GF(2): the UMI merges multiplier and inverter into one unified data-path. As such, the area of the data-path is reduced. We present two options for hyperelliptic curve cryptography (HECC) using UMIs: an FPGAbased high-performance implementation (Type-I) and an ASIC-based lightweight implementation (Type-II). The use of a UMI combined with affine coordinates brings a smaller data-path, smaller memory and faster scalar multiplication. Both implementations use curves defined by h(x)1⁄4x and f ðxÞ 1⁄4 x5þ f3xþxþ f0. The high throughput version uses 2316 slices and 2016 bits of block RAM on a Xilinx Virtex-II FPGA, and finishes one scalar multiplication in 311 ms. The lightweight version uses only 14.5 kGates, and one scalar multiplication takes 450 ms. & 2011 Elsevier B.V. All rights reserved.